Memory-system Design Considerations

Memory-System Design Considerations for Dynamically-Scheduled Microprocessors Keith Istvan Farkas Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 1997 Dynamically-scheduled processors challenge hardware and software architects to develop designs that balance hardware complexity and compiler technology against performance targets. This dissertation presents a first thorough look at some of the issues introduced by this hardware complexity. The focus of the investigation of these issues is the register file and the other components of the data memory system. These components are: the lockup-free data cache, the stream buffers, and the interface to the lower levels of the memory system. The investigation is based on software models. These models incorporate the features of a dynamically-scheduled processor that affect the design of the data-memory components. The models represent a balance between accuracy and generality, and are used to identify performance trends and design relationships rather than to evaluate the performance of specific designs. The models are used to identify and explore the relationships between the following system aspects: the dispatch queue, the physical registers, the type of exceptions, the issue width of the processor and the number of functional units, the lockup-free data cache, the stream buffers, and the interface to the lower levels of the memory system. Implementation-related relationships are exposed through an analysis of how various design decisions impact the cycle time of a register file. Following from this analysis, an investigation of a novel architecture is conducted. The novelty of this architecture is the partitioning of key components to reduce the cycle time of the processor. A comprehensive examination is given of the software and hardware complexities the partitioning introduces.